DESIGN OF A FOUR STAGES VCO USING A NOVEL DELAY CIRCUIT FOR OPERATION IN DISTRIBUTED BAND FREQUENCIES

The manuscript proposes a novel architecture of a delay cell that is implemented in 4-stage VCO which has the ability to operate in two distributed frequency bands. The operating frequency is chosen based on the principle of carrier mobility and the transistor resistance. The VCO uses dual delay input techniques to improve the frequency of operation. The design is implemented in Cadence 90nm GPDK CMOS technology and simulated results show that it is capable of operating in dual frequency bands of 55 MHz to 606 MHz and 857 MHz to 1049 MHz. At normal temperature (270) power consumption of the circuit is found to be 151μW at 606 MHz and 157μW at 1049 MHz respectively and consumes an area of 171.42µm2. The design shows good tradeoff between the parameters-operating frequency, phase noise and power consumption

Low Leakage Low Power Domino Logic Technique for Wide Fan-In Applications, 40-Bit Tag Comparator: Domino based TAG Comparator

Advances in sub-micron technologies make low power consumption and delay a major concern for present day systems. These parameters play a critical role in the performance of most widely used wide fan-in- dynamic logic gates. These wide fan-in dynamic gates are employed in designing high speed tag comparators which are critical blocks of cache memory. The proposed technique tries to have an insight on a 40-bit tag comparator in terms of power consumption and noise immunity to produce a high performance logic style. The approach limits the voltage swing at the dynamic node with the help of stack transistor employed between dynamic node and clocked bleeder transistor. This technique will reduce the overall power consumption and improves the gate speed for constant noise immunity. The observation is carried out with 1 GHz clock frequency and 0.9 V supply at 27 0C temperature using Cadence Virtuoso Spectre and Layout editor for 90 nm CMOS technolog

Low Leakage Low Power Domino Logic Technique for Wide Fan-In Applications, 40-Bit Tag Comparator: Domino based TAG Comparator

Advances in sub-micron technologies make low power consumption and delay a major concern for present day systems. These parameters play a critical role in the performance of most widely used wide fan-in- dynamic logic gates. These wide fan-in dynamic gates are employed in designing high speed tag comparators which are critical blocks of cache memory. The proposed technique tries to have an insight on a 40-bit tag comparator in terms of power consumption and noise immunity to produce a high performance logic style. The approach limits the voltage swing at the dynamic node with the help of stack transistor employed between dynamic node and clocked bleeder transistor. This technique will reduce the overall power consumption and improves the gate speed for constant noise immunity. The observation is carried out with 1 GHz clock frequency and 0.9 V supply at 27 0C temperature using Cadence Virtuoso Spectre and Layout editor for 90 nm CMOS technolog